Non-volatile memory cells, including stacked gate and split gate, are well-known in the art. The split gate structure has better over erase control performance, simple circuit design and faster access speed.
A cross section of a conventional Flash EEPROM is shown in FIG. 1. Drain impurity diffusion layer 16 and a source impurity diffusion layer 17 are formed on a main surface of the semiconductor substrate 10 and are spaced from each other by a predetermined distance with a channel region therebetween. The conventional Flash EEPROM further includes a floating gate electrode 13 formed on the channel region with a first gate oxide film 12 therebetween, a control gate electrode 15 formed on the floating gate electrode 13 with an insulating film 14 therebetween, an interlayer thermal oxide film 18 covering the semiconductor substrate 10, floating gate electrode 13 and control gate electrode 15, and an interlayer insulating film 19 covering the interlayer thermal oxide film 18. Gate bird's beak oxide films 20 are formed at opposite ends of the first gate oxide film 12 and opposite ends of the insulating film 14. The interlayer insulating film 19 contains an impurity such as boron or phosphorous. The purpose of the interlayer thermal oxide film 18 is to prevent the movement of the impurity (i.e., boron of phosphorous) of the interlayer insulating film 19 into the semiconductor substrate 10, control gate electrode 15 or floating gate electrode 13, and thus to prevent change of the electrical characteristics thereof.
After the final step of forming the interlayer insulating film 19 to cover the interlayer thermal oxide film 18 shown in FIG. 1, heat treatment by a reflow method is usually carried out to flatten the interlayer insulating film 19. During this process as well as while thermally growing the thermal oxide layer 18 by means of wet oxidation, oxidizer (H.sub.2 O) penetrates the interlayer insulating film 19 and interlayer thermal oxide film 18. This causes further oxidization between the semiconductor substrate 10 and the ends of the floating gate electrode 13, and between the control gate electrode 15 and the floating gate electrode 13. As a result, the gate bird's beak oxide films 20 are formed. Consequently, the lower end of the floating gate electrode 13 contacts the gate bird's beak oxide films 20 so that the lower end of the floating gate electrode 13 is oxidized to a large extent as compared with the other portions.
The gate bird's beak oxide film 20 can form either at the lower end of the floating gate 13 and the source impurity diffusion layer 17, or at the lower end of the floating gate near the drain impurity diffusion layer 16, or at both locations. In these cases, the conventional "beak" of the bird's beak is usually long and elongated, thus increasing the size of the cell and at the same time providing paths for current leakage and resulting, therefore, in low memory speed.
The formation of a conventional bird's beak in a polysilicon gate is better shown in FIGS. 1b and 1c. In FIG. 1b, layers of gate oxide 110, polysilicon 120 and nitride 130 are successively formed on substrate 100 and then patterned with a photomask layer 140 to define the floating polygate region 160. Subsequently, polysilicon layer 120 is oxidized, whereby gate bird's beaks 121 and 121' are formed as well known in the art. The prior art offers a method of implanting the polysilicon so as to decrease the growth of the protrusion of the gate bird's beak as shown by reference numerals 121 and 121' in FIG. 1c to a smaller size and sharper shape shown by reference numerals 125 and 125'. It will be known by those skilled in the art that the smaller the birds' beak, the smaller the encroachment under the polysilicon edge, and hence the smaller the impact on the electric-field intensity between the corner edge of the floating gate 129 and the control gate 180 of the completed cell structure shown in FIG. 1d, and thus the faster the memory speed. (See S. Wolf and R. N. Tauber, "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, Calif., 1990, p. 438). It will also be appreciated that the smaller the bird's beak, the smaller the overall size of the memory cell, also contributing to the increased speed of the memory.
However, in the above-mentioned prior art, it is difficult to reduce the chip area occupied by the memory cells because all of the cells are built on the silicon surface.